Anirban Sengupta

Short CV: Anirban Sengupta is currently a full Professor in Dept of CSE at Indian Institute of Technology Indore, where he joined in 2012. He has been Visiting Scientist at Advanced Computing and Microelectronics Unit at ISI Kolkata and Visiting Scholar at SERC, IISc Bangalore earlier. He is IEEE Distinguished Visitor of IEEE Computer Society, IEEE Distinguished Lecturer of IEEE Consumer Technology Society and ACM India Eminent Speaker. He is Fellow of IET, Fellow of British Computer Society, Fellow of IET, Fellow of IETE. He has over 320 publications and patents and won over 8 IEEE awards including prestigious IEEE Chester Sall Memorial Consumer Electronics Award by IEEE Technical Activities Board, in Las Vegas in 2020. He is also the former chair of IEEE Computer Society TC-VLSI and former chair of IEEE Consumer Technology Society Security and Privacy Committee (SPC).

Title of Talk 1: Anti-Piracy aware Hardware IP Design using High Level Synthesis (HLS)

Synopsis: Intellectual property (IP) designs are indispensable components of consumer electronics (CE) products such as set-top boxes, digital TVs, DVDs, tablets, digital cameras, audio-video receivers etc. IP chipsets represent several man years of investment, research and development through expensive infrastructure. Watermarking in IP chipsets for protection of CE devices against false claim of ownership, piracy and counterfeit has been proved as a promising solution. However, the design process of a watermarked (anti-piracy aware) IP chipset is complex and no published work exists in the literature to introduce a formal design methodology. This paper presents a formal design approach for anti-piracy aware IP chipsets for CE devices. Using robust multi-variable signature encoding methodology, decoded watermarking constraints are embedded into the formal architectural synthesis design steps of an IP chipset. Each step of the IP chipset design will be lucidly introduced with the aid of a real life benchmark from the domain of multimedia and digital signal processing

Title of Talk 2: High Level Synthesis (HLS) based IP Core Protection 

Synopsis: The current design era of consumer electronics is reliant on global IC supply chains. To maximize design productivity and minimize design time, the use of intellectual property (IP) cores, often supplied by a third party vendor, has become standard practice in the industry. However there are increasing threats to security, and growing piracy issues that threaten global supply chains as system-on-chip design becomes increasingly commoditised. As a consequence the requirements for protection of IP-core designs and the know-how they represent has become of importance to industry. This topic provides an insight into this challenge faced by many CE manufacturers and an overview of current and past methodologies. The pros and cons of each approach and some practical cases studies will help understand this challenge. Some consideration is also given to the potential future evolution of IP protection

Title of Talk 3: Hardware Security: Threat Models and Defense against IP Trojans and IP Piracy 

Synopsis: This topic will delve deep into the threat models and defense mechanisms against hardware Trojans and IP piracy. This topic discusses hardware security of consumer electronics (CE) devices, focusing primarily on threat models and defense mechanisms against two major attacks: hardware Trojans and IP piracy. Further, other hardware related IP attacks on CE design will be discussed along with its security mechanism. Design for security will be emphasized for CE community designers and practitioners who focus on IP core security.